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华夏芯发布领先的CPU/DSP处理器IP和AI专用处理器IP
华夏芯发布领先的CPU/DSP处理器IP和AI专用处理器IP

2018-02-01

ICCAD 2019抢先看——参展IP公司介绍
ICCAD 2019抢先看——参展IP公司介绍

2019-11-19

Zhuhai Chuangfeixin Antifuse eFPGA IP
Zhuhai Chuangfeixin Antifuse eFPGA IP

2019-10-17

CFX announces ISO9001 Certification
CFX announces ISO9001 Certification

2019-10-17

CFX announces commercial availability of anti-fuse OTP technology on SMIC 55HV process
CFX announces commercial availability of anti-fuse OTP technology on SMIC 55HV process

2019-09-18

IBM正式开源POWER处理器指令集,应对RISC-V
IBM正式开源POWER处理器指令集,应对RISC-V

2019-08-21

阿里平头哥首次交货!“让天下没有难造的芯片”
阿里平头哥首次交货!“让天下没有难造的芯片”

2019-07-25

ARM启用新的授权费模式:每年支付20万美元,就可获得不限数量的芯片设计方案
ARM启用新的授权费模式:每年支付20万美元,就可获得不限数量的芯片设计方案

2019-07-18

流片信息

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知识园地

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EMC电磁兼容的共模干扰与差模干扰是什么,又该如何抑制呢?
EMC电磁兼容的共模干扰与差模干扰是什么,又该如何抑制呢?

2019-03-11

关于MCU,没有比这一篇更全了
关于MCU,没有比这一篇更全了

2018-01-31

数字验证的sign off验收标准
数字验证的sign off验收标准

2018-01-31

【中天微】在线技术论坛v1.0正式上线
【中天微】在线技术论坛v1.0正式上线

2018-01-31

谈谈SOC复位那点事儿
谈谈SOC复位那点事儿

2018-01-30

IP目录

  • E-mail E-mail

    • LDO

    Portable/Battery-Powered Equipment Point of Load Regulation for DSPs, FPGAs, ASICs, and Microprocessors

  • E-mail E-mail

    • LDO

    Portable/Battery-Powered Equipment Point of Load Regulation for DSPs, FPGAs, ASICs, and Microprocessors

  • E-mail E-mail

    • LDO

    40nm, Input Voltage Range of 2.1V to 2.9V, Fixed Output Voltage 1.1V

  • E-mail E-mail

    • Digital PLL

    55nm, Single 1.2V power supply required, Fully integrated PLL-based clock generator including loop filter

  • E-mail E-mail

    • Digital PLL

    40nm, Single 1.1V power supply is required, Fully integrated PLL-based clock generator including loop filter

  • E-mail E-mail

    • Low jitter PLL

    40nm, Both 2.5V and 1.1V power supplies are required, Fully integrated PLL-based clock generator including loop filter

  • E-mail E-mail

    • PLL

    110nm, Fully integrated PLL-based clock generator including loop filter, Required voltage of 1.2/3.3v

  • E-mail E-mail

    • 3 channel Video AFE

    180nm, 1.8V and 3.3V power supplies required, 3-Channel AFE with shared internal reference generator.

  • E-mail E-mail

    • Video AFE

    55/65nm, 12-bit 165 MHz ADC, Programmable Gain Amplifier

  • E-mail E-mail

    • Video AFE

    180nm, Power supplies of 1.8V and 5.0V are required, 3-Channel AFE with shared single reference block.

  • E-mail E-mail

    • 3-channel multi-format AFE

    55nm, Channel 12-bit 165MSPS ADC, Single-ended Input with Fully differential Internal Processing

  • E-mail E-mail

    • 10-bit Dual Channel DAC

    180nm, High speed current steering architecture, Dual channel matched analog outputs

  • E-mail E-mail

    • 10-bit DAC

    180nm, Two Identical Channels, 10-bit Resolution

  • E-mail E-mail

    • 14-bit DAC

    180nm, 3.3V analog and 1.2V digital supply, Differential output swing: -1.0V to +1.0V

  • E-mail E-mail

    • 12-bit DAC

    55nm LL CMOS logic process without any mixed mode options.

  • E-mail E-mail

    • 10-bit DAC

    65nm, Dual +1.2V/+3.3V power supplies required, Very small silicon area of 350um x850um with 1P7M layout structure.

  • E-mail E-mail

    • 10-bit SAR ADC

    55nm, Time interleaved architecture for excellent dual channel matching performance.

  • E-mail E-mail

    • 8-bit SAR ADC

    65nm, Time interleaved architecture for excellent dual channel matching performance.

  • E-mail E-mail

    • 12-bit pipeline ADC

    130nm, 3.3V analog supply and 1.2V digital supply operation

  • E-mail E-mail

    • Dual Channel 10B50M ADC

    55nm/65nm, 55nm GP CMOS logic process with low threshold voltage devices.

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